1. Field of Invention
The present invention relates to a semiconductor device structure and fabrication of the same, and more particularly, to a metal-oxide-semiconductor (MOS) transistor structure and a method for fabricating the same.
2. Description of Related Art
MOS transistors are essential elements in VLSI or ULSI circuit products, which include microprocessors, semiconductor memory devices and power devices, etc.
In a nanometer-scale MOS process, usually, a trench is formed in the substrate beside the gate structure and then filled by a strained doped epitaxial layer as a source/drain (S/D), so as to improve the electron mobility or hole mobility. More specifically, in such a MOS process, a gate structure is formed with a hard mask layer thereon for protection in later steps, a spacer is formed on the sidewall of the gate structure, and a trench is formed in the substrate beside the spacer through lithography and etching. A pre-cleaning step is conducted to remove native oxide and etching residues from the trench, and a doped epitaxial layer is formed in the trench as the S/D or a part thereof.
However, since the etching steps for the spacer and the trench, the photoresist removal and the pre-cleaning step all damage the hard mask layer on the gate structure, the surface of the gate structure is easily exposed. If the surface of the gate structure is exposed, a polysilicon bump will be formed on the exposed portion of the poly-Si gate during the epitaxy process for forming the strained doped epitaxial layer. The poly-Si bump significantly lowers the reliability and the performance of the device.